1. Field of the Invention
The present invention relates to an output buffer circuit for use in an integrated semiconductor circuit device, and more particularly to an output buffer circuit which is capable of adjusting the output impedance thereof according to control signals from an external source.
2. Description of the Related Art
Systems incorporating integrated semiconductor circuit devices in recent years employ memory devices such as DRAMs (Dynamic Random Access Memories) and SDRAMs (Synchronous DRAMs) which operate with a clock signal of several hundreds MHz as a result of processing operations at higher speeds. To meet lower power consumption requirements, there are also available integrated semiconductor circuit devices that operate at lower power supply voltages of about 1.5 V or lower.
It is important for systems operating at higher speeds and under low voltages to suppress variations in the driving capability and slew rate of the output buffer circuit of the integrated semiconductor circuit device in view of fluctuations in the power supply voltage and the ambient temperature and different device performance capabilities.
For example, Japanese patent applications laid-open Nos. 05-175444 and 2-092019 propose arrangements for adjusting the driving capability of an output buffer circuit by changing the output impedance thereof. Proposals disclosed in Japanese patent applications laid-open Nos. 2001-68986 and 2000-332593 adjust the slew rate of an output buffer circuit by changing the ratio of tr(rise time)/tf(fall time) of an output pulse waveform.
Integrated semiconductor circuit devices such as DDR (Double Data Rate)-SDRAMs receive data from a memory device which outputs data in timed relation to rising and falling edges of a system clock signal CLK (see FIG. 1 of the accompanying drawings). In such an integrated semiconductor circuit device, if the timing to sent data (a cross-point CP between rising and falling waveforms shown in FIG. 1) is shifted a one-half period (tck/2) from the system clock signal CLK, then the integrated semiconductor circuit device fails to receive the transmitted data correctly. Actual systems have a very narrow range (window) of allowable cross-point variations because of delays caused by interconnections, etc.
If the slew rate becomes lower, then since the amplitude of output pulses cannot reach a maximum value when the system operates at a high speed, the system fails to determine a logic level of “1” or “0” properly. Conversely, if the slew rate become higher, then high-frequency components increase to distort output pulses, thus increasing noise which tends to result in a system malfunction.
The above problems may be solved by compensating for variations in the cross-point CP and the slew rate at the data transmission side. However, variations in the cross-point CP and the slew rate cannot be compensated for simply by adjusting the output impedance. Only adjusting the slew rate fails to achieve a compensation within the allowable range of variations of the system which operates at a high speed and under a low voltage because the cross-point CP and the slew rate depend on variations of both the output impedance and the power supply voltage.
In particular, if only the slew rate is adjusted, when the high level of the output signal is lowered or the low level of the output signal is increased due to a reduction in the driving capability, the system becomes unable to determine a logic level of “1” or “0” properly.
The output impedance of an output buffer circuit can easily be detected for fluctuations by monitoring the load current and output level of the output buffer circuit even when the output buffer circuit is incorporated in a system. However, it is difficult to detect fluctuations of the slew rate of the output buffer circuit because the slew rate cannot easily be monitored.
The output buffer circuits disclosed in the above applications offer an arrangement for adjusting either one of the output impedance and the slew rate, and are disadvantageous in that variations in the cross-point CP and the slew rate of the disclosed output buffer circuits as they are incorporated in a system cannot sufficiently be compensated for against variations in the power supply voltage and the ambient temperature.
Controlling the cross-point and the slew rate needs to take the following problems into account:
Generally, systems having integrated semiconductor circuit devices such high-speed DDR-DRAMs or the like employ a phase synchronizing circuit such as a DLL (Delay Locked Loop) or a PLL (Phase Locked Loop) in order to synchronize data output from the output buffer circuit of the integrated semiconductor circuit device with the system clock signal. The phase synchronizing circuit uses a circuit having a delay similar to the delay in the output buffer circuit for monitoring the delay in the output buffer circuit. The phase synchronizing circuit generates a compensating clock signal for compensating for the monitored delay, and synchronizes the output from the output buffer circuit with the generated compensating clock signal.
If the output impedance and the slew rate of the output buffer circuit are adjusted to improve the system performance, then the data output timing of the output buffer circuit varies because of the adjustment of the output impedance and the slew rate thereof.
In order to synchronize the data output timing of the output buffer circuit accurately with the system clock signal, therefore, it is necessary for the circuit which monitors the delay in the output buffer circuit to adjust its own delay depending on variations in the delay in the output buffer circuit.